asic layout Design EngineerCông Ty TNHH Bosch Global Software Technologies
Hình thức: Toàn thời gian
Ngày đăng: 05/03/2024
Hạn nộp: 04/04/2024
Vị trí công việc này hiện tại đã hết hạn nộp hồ sơ, bạn có thể tham khảo thêm một số công việc tương tự tại đây:
Mô tả công việc
Mô tả công việc
Tóm tắt công việc
As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor.
- You will work with international design team to ensure the layout delivery on time and in quality, then execute whole tape-out flow together with wafer foundry.
- You will Work with digital backend engineer to generate DFE file for P&R and integrated digital layout into whole chip.
- You will also work with CAD engineers to continuously improve our PDKs and design environment.
Tóm tắt công việc
As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor.
- You will work with international design team to ensure the layout delivery on time and in quality, then execute whole tape-out flow together with wafer foundry.
- You will Work with digital backend engineer to generate DFE file for P&R and integrated digital layout into whole chip.
- You will also work with CAD engineers to continuously improve our PDKs and design environment.
Yêu cầu công việc
Yêu cầu công việc
1. Required Skills and Experience
- Bachelor/master's degree majored in microelectronics or relevant electrical engineering field (main course: a analog circuits, digital circuits, semiconductor device and physics, semiconductor manufacturing).
- Experience in analog/mix-signal integrated circuit layout for ADCs, DACs, PLLs, LDOs, Charge pump, bandgap design
- In-depth knowledge of TSMC28nm - 152nm, SMIC110nm, TZ 180nm BCD SOI technologies and design rules
- Solid knowledge of industry standard IC layout conventions and rules for reducing layout risk
- Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools Calibre, PVS, Assura, etc.
- Understanding of CMOS process side effect and known how to minimize the risk in layout (e.g.lithographic mismatch, LOD effect, WPE effect, latch-up, ESD, antenna, density stress, etc...)
- Be able to analysis EM and IR drop
- Skilled in Linux operating system
- Strong problem-solving skills
- Fluent English in writing and speaking.
2. Preferred Skills and Experience
- Work experience in an international company or abroad
- Programming: shell, skill, python, tcl.
- Experience in leading a full chip layout from floorplan to tape-out
- Auto place and route experience for non-timing critical design is a plus
1. Required Skills and Experience
- Bachelor/master's degree majored in microelectronics or relevant electrical engineering field (main course: a analog circuits, digital circuits, semiconductor device and physics, semiconductor manufacturing).
- Experience in analog/mix-signal integrated circuit layout for ADCs, DACs, PLLs, LDOs, Charge pump, bandgap design
- In-depth knowledge of TSMC28nm - 152nm, SMIC110nm, TZ 180nm BCD SOI technologies and design rules
- Solid knowledge of industry standard IC layout conventions and rules for reducing layout risk
- Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools Calibre, PVS, Assura, etc.
- Understanding of CMOS process side effect and known how to minimize the risk in layout (e.g.lithographic mismatch, LOD effect, WPE effect, latch-up, ESD, antenna, density stress, etc...)
- Be able to analysis EM and IR drop
- Skilled in Linux operating system
- Strong problem-solving skills
- Fluent English in writing and speaking.
2. Preferred Skills and Experience
- Work experience in an international company or abroad
- Programming: shell, skill, python, tcl.
- Experience in leading a full chip layout from floorplan to tape-out
- Auto place and route experience for non-timing critical design is a plus
Thông tin khác
Yêu cầu kỹ thuật:
Shell Script
,
Python
,
ADC
,
Linux
,
Cadence
,
LDO
Shell Script
,
Python
,
ADC
,
Linux
,
Cadence
,
LDO
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Công Ty TNHH Bosch Global Software Technologies
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Vị trí asic layout Design Engineer do công ty Công Ty TNHH Bosch Global Software Technologies tuyển dụng tại Hồ Chí Minh, Joboko tự động tổng hợp mức lương Thỏa Thuận, tìm thêm việc làm về ASIC Layout Design Engineer hoặc công ty Công Ty TNHH Bosch Global Software Technologies ở các link phía trên
Giới thiệu công ty
Công Ty TNHH Bosch Global Software Technologies việc làm
Etown2, 364 Cộng Hòa, Phường 13, Quận Tân Bình, Thành phố Hồ Chí Minh
Quy mô: Từ 501 - 1000 nhân viên