Responsibilities
Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.
Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual
tester environments.
Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.
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XNote: By applying to this position you will have an opportunity to share your preferred working location from the following: San Diego, CA, USA; Mountain View, CA, USA.
Minimum qualifications:
Bachelor's degree in
Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.
Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.
Experience in RTL verification and Gate Level Simulation (GLS) workflows.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with UVM/OVM methodologies and using Python or Perl to automate ARM SoC verification flows.