Job title: Design Verification Engineer
Level: Senior/Staff/Principle
Location: Ho Chi Minh City & Da Nang City, Vietnam
Responsibilities
Write verification plans and drive functional coverage closure (code, functional, assertion coverage)
Develop UVM-based testbenches, sequences, and scoreboards for IP/subsystem/SoC-level verification
Apply formal property verification for exhaustive coverage of ownership, ordering, and protocol correctness, complementary to simulation-based verification
Build SystemC or transaction-level performance/architecture models to support pre-RTL design space exploration and architecture decisions
Develop performance verification methodology - bandwidth, latency, arbitration/QoS, and stress/corner-case scenarios
Debug RTL and testbench issues; triage failures with DE and architecture teams
Participate in design/verification reviews and produce clear documentation of test plans, coverage, and sign-off criteria
Requirements
Bachelor's or Master's degree in
Electrical Engineering, Computer Engineering, or related field
Hands-on experience with UVM methodology and SystemVerilog verification environments
Experience with formal verification tools and writing SVA properties/assertions
Experience building SystemC, C/C++, or Python-based performance/transaction-level models
Solid understanding of functional coverage, constrained-random verification, and coverage-driven closure
Familiarity with at least one of the following domains:
Bus protocols (AXI/AHB/APB/CHI) and cache/coherency architectures
CPU (ARM, RISC-V), GPU, or NPU architectures
DMA, memory subsystem, or shared SRAM/banked memory verification
High-speed IO (PCIe/UCIe/Ethernet/USB/etc.) or memory (DDR/HBM) verification
Good communication skills; comfortable working across distributed global teams