Minimum qualifications:
Bachelor's degree in
Electrical Engineering, Computer Science, or equivalent practical experience.
15 years of experience in front-end design or design verification.
Experience in power-aware verification methodologies.
Experience in fabric and interconnect architectures and cache coherency protocols.
Preferred qualifications:
Master's degree in Electrical Engineering or Computer Science or equivalent practical experience.
Experience in verification of high-bandwidth memory subsystems (DDR5, LPDDR5, HBM) including physical layer (PHY) training, memory controllers, and JEDEC compliance.
Extensive experience directly managing high-performing engineering teams with a proven track record of successfully delivering complex, production-grade SoCs.
Technical expertise in SoC-level verification and strong design verification (DV) fundamentals using universal verification methodology (UVM)-based environments. Direct Experience with pre-silicon emulation platforms and hardware accelerators (e.g., SimXL, formal verification, or portable stimulus standard/PSS).
Strong programming skills in SystemVerilog, Verilog, and scripting languages like Python or Perl.