Testbench Development: Build and maintain functional test environments and testbenches using SystemVerilog and UVM frameworks.
Test Planning & Execution: Handle pre-silicon test planning and execution at the IP or block level to prove out chip designs before production.
Metrics & Failure Analysis: Develop coverage-driven verification structures and assertion models (SVA) to ensure design reliability.
Design Collaboration: Review product designs alongside chip
designers to identify potential points of failure and understand communication protocols.
Automation: Write simple verification scripts to automate test flows and improve overall engineering efficiency.
Hands-on Verification Experience: Real, practical experience handling digital IC verification (specifically at the block or IP level).
Language Fluency: Solid, practical proficiency with SystemVerilog and UVM testbench environments.
Methodology: Familiarity with coverage-driven and assertion-based verification.
Adaptability: A strong engineering mindset with a desire to learn advanced methodologies (like UPF or formal verification) on the job.
Nice to Have:
Exposure to power-aware verification (UPF), formal verification, or scripting (Python/Perl).
Experience with Power IP, analog/mixed-signal, or automotive-grade chips.
Ground-Floor Impact: Be one of the foundational members of a brand-new Vietnam engineering center with excellent long-term career growth.
On-the-Job Learning: Clear paths to pick up highly specialized semiconductor skills like advanced formal methods and power-aware (UPF) validation workflows.
Flexible Work Model: Secure, long-term employment via a premium Employer of Record (EOR) structure with 100% remote work flexibility (while staying connected to a localized hub of peers in HCMC).