• Design and implement layout for analog and digital circuit cells and blocks.
• Perform floorplanning for cells, blocks, and full-chip layouts, including signal routing strategy.
• Optimize layout parasitics based on schematic requirements and circuit performance.
• Perform physical verification and checking, including DRC, LVS, ERC, ANT, ESD, and PEX.
• Prepare and verify full-custom IC GDS files for tape-out to foundries, including mask generation checks.
QUALIFICATIONS & EXPERIENCE
• Bachelor's degree or higher in
Electrical Engineering, Electronics Engineering, Microelectronics, or a related field.
• Self-motivated and able to work independently on assigned projects.
• Strong teamwork and communication skills, with the ability to collaborate across layout and other engineering teams.
• Good problem-solving and debugging skills.
• Familiarity with Cadence Virtuoso Custom IC Design tools and Linux/Unix environments is a plus.
• Experience with physical verification using Siemens Calibre, including parasitic extraction, is a plus.
BENEFITS
• Competitive salary based on personal capacity and experience. Performance review to adjust salary.
• Working full time 5 days per week, not include Saturday & Sunday.
• Dynamic workplace, technology environment.
• Oversea training opportunity.
• Other side benefits such as compulsory insurance based on full salary, lunch allowance, annual health-screen, sport activities, outing activities, team building...