LAYOUT DESIGN ENGINEER

Perform cell and chip-level schematic entry, IC layout, and verification (LVS, DRC, ERC).
Chip floorplanning and I/O ESD routing, and support/assist in tapeout and documentation.
Collaborate with design engineers to prepare IC layouts for tapeout on technologies such as CMOS, SOI, SiGe, and BICMOS.
Use revision control systems for design database management.
Create documentation.
PDK modification and SKILL scripting for design and CAD teams to support layout flows is a plus.