Alternate Job Titles
Staff Memory Layout Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in the trenches of memory layout, where a single transistor out of place can mean the difference between a chip that ships and one that doesn't. SRAM, ROM, eDRAM, you know these structures at the cell level, not just conceptually but in the way you know a tool you have used every day for years. You understand that memory layout is not just about fitting shapes into a grid. It is about balancing area, yield, performance, and manufacturability in a space where every nanometer counts.
When a DRC violation shows up late on a Friday, you do not panic. You dig in, trace it back, and figure out whether it is a real problem or a rule deck quirk. Working with circuit
designers, process engineers, and verification teams does not slow you down.
It sharpens your work because you know that the best layouts come from understanding what everyone else needs. Being a staff engineer means more than being the best at layout. It means helping others get better, sharing what you have learned, and making the people around you stronger.
What You'll Be Doing
Lead physical layout design for advanced memory IP including SRAM, ROM, and eDRAM at the cell, array, and peripheral circuit levels
Ensure every layout meets foundry process design rules and memory-specific constraints, resolving DRC and LVS issues with precision
Optimize layouts for area efficiency, performance targets, power consumption, yield improvement, and manufacturability
Perform RC extraction and parasitic analysis on dense memory arrays, then iterate to improve signal integrity and timing margins
Debug complex layout issues including electromigration, IR drop, and soft error susceptibility with reliability teams
Collaborate with circuit designers, verification engineers, and process teams to deliver first-pass silicon success
Mentor junior layout engineers on best practices, tool usage, and design tradeoffs
The Impact You Will Have
Deliver memory IP that powers chips for AI, mobile, automotive, and high-performance computing at leading tech companies
Reduce risk and accelerate time to market with layouts that are correct, optimized, and manufacturable before tapeout
Drive innovation in layout techniques and automation that improve efficiency and quality across the memory IP portfolio
Elevate team capability by sharing knowledge and setting the standard for excellent layout work
Strengthen Synopsys' position as the leader in memory IP with products customers depend on for critical projects
Enable customer innovation by providing memory solutions that meet aggressive performance, power, and area requirements
What You'll Need
Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or a related technical field
At least 5 years of hands-on experience in custom layout design with significant focus on memory structures like SRAM, ROM, or eDRAM
Deep expertise in memory layout at the transistor and cell level, including array structures, sense amplifiers, decoders, and peripheral circuits
Proficiency with layout tools such as Custom Compiler, Virtuoso, or IC Compiler for physical design and verification
Strong working knowledge of foundry process design rules, DRC/LVS verification flows, and memory-specific layout constraints
Experience performing RC extraction, analyzing parasitic effects, and iterating layouts to meet signal integrity requirements
Who You Are
You approach every layout with a detail-oriented mindset, knowing that small mistakes in dense memory structures cascade into big problems
Collaboration comes naturally. You synthesize input from circuit designers and process engineers into better layouts
When something is not working, you dig in analytically, isolate variables, test hypotheses, and document what you learn
You take initiative to improve processes and tools without waiting for permission
Mentoring is not a checkbox. You genuinely enjoy helping engineers understand why layout choices matter
The Team You'll Be Part Of
You will join the memory layout team in Da Nang, a group dedicated to delivering high-quality, high-performance memory IP that powers next-generation semiconductor products. The team works on some of the most challenging IP in the Synopsys portfolio, collaborating across global sites with circuit designers, verification engineers, and customers.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.