Physical Design Engineer (HCM - Attractive Salary)

Position Overview
We are seeking a Physical Design Engineer responsible for executing and owning the RTL to GDSII implementation flow for ASIC/SoC designs. The role includes floorplanning, place & route, timing closure, power integrity, and physical verification, ensuring high quality, tape out ready silicon.
Note: This position is open to qualified candidates located anywhere in Vietnam; remote or hybrid working arrangements can be considered depending on the role and project needs.
Key Responsibilities
• Execute complete RTL / Gate level Netlist to GDSII flow for blocks or full chip.
• Ownership of physical implementation of design partitions/blocks. Responsible for delivering timing clean blocks that meet sign-off targets including DRC, LVS & IR closure for tape out readiness.
• Floor planning & Power Planning
• Timing Closure & STA
• CTS & Signal Integrity
• Physical Verification & Sign off