pre silicon - design verification Engineer

Requirements:
The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 3 years experience in digital ASIC/SOC design verification.
The candidate should have good understanding on ASIC/SOC design flow and should have:
1. Strong coding with Verilog and SystemVerilog
2. Good knowledge of design verification methodology UVM.
3. Many experiences with sequence creation, functional cover groups and assertion coding.
4. Strong C/C++ software development experiences
5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.
A plus:
- Has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.