IP/SOC design verification
Assist in the design and implementation of RTL for integrated circuits under the guidance of senior
engineers
Support floor planning, power planning, placement, routing, and physical verification activities.
Participate in timing closure and signal integrity analysis processes to ensure design reliability.
Collaborate closely with RTL
designers, verification engineers, and technology teams to optimize design
methodologies.
Contribute to the development and maintenance of design methodologies, automation flows, and
scripts.
Engage in design reviews, debugging tasks, and problem-solving activities to meet project timelines.
Pursuing or recently completed a Bachelor's degree in
Electrical Engineering, Computer Engineering, or a related field.
Familiarity with RTL design concepts and methodologies.
Basic knowledge of industry-standard CAD tools such as Cadence, Synopsys, or Mentor Graphics for RTL design.
Exposure to scripting languages like Tcl, Python, or Perl for automation and design flow development.
Understanding of ASIC design flow, semiconductor process technology, and low-power design techniques.