Assist with IP/SoC RTL design, integration, implementation, and verification under the guidance of senior engineers.
Assist in the design and implementation of RTL for integrated circuits under the guidance of senior engineers.
Gain exposure to the physical design flow-including floorplanning, power planning, placement, routing, timing closure, signal integrity analysis, and physical verification-while collaborating with implementation teams.
Collaborate closely with RTL
designers, verification engineers, and technology teams to optimize design methodologies.
Contribute to the development and maintenance of design methodologies, automation flows, and scripts.
Engage in design reviews, debugging tasks, and problem-solving activities to meet project timelines.
Currently pursuing or recently completed a Bachelor's degree in
Electrical Engineering, Computer Engineering, or a related field...
Familiarity with digital design fundamentals, RTL design concepts, and Verilog or SystemVerilog; exposure to simulation, linting, synthesis, CDC/RDC analysis, or formal verification is an advantage.
Basic familiarity with industry-standard EDA tools from vendors such as Cadence, Synopsys, or Siemens EDA for RTL simulation, linting, synthesis, or verification.
Exposure to scripting languages like Tcl, Python, or Perl for automation and design flow development.
Understanding of ASIC design flow, semiconductor process technology, and low-power design techniques.
Comfortable using English in a professional working environment.
Experience using AI-assisted engineering tools responsibly for learning, coding, debugging, documentation, or workflow automation is a plus.
Familiarity with high-speed interfaces such as UCIe, PCIe, or DRAM, or with multimedia IP such as CSI, ISP, DSP, or GPU, is a significant advantage.