Senior Allegro PCB Layout Design Engineer

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• Design, develop, and optimize high-speed, high-density PCB layouts using Cadence Allegro and OrCAD.
• Collaborate closely with hardware, SI/PI, mechanical, and system engineers to define layout requirements and design constraints.
• Support and incorporate Signal Integrity (SI) and Power Integrity (PI) analysis to ensure robust electrical performance.
• Implement advanced layout techniques for DDR4 and 50G SERDES high-speed interfaces.
• Ensure compliance with EMC/EMI, manufacturability (DFM), and reliability standards throughout the design process.
• Review, validate, and maintain design documentation, ensuring accuracy and adherence to internal and industry standards.
• Identify, troubleshoot, and resolve complex layout and performance issues from concept through production.
• Provide technical leadership and mentorship to junior PCB layout engineers, promoting best practices and design excellence.