Date posted [protected info]
Category Engineering*Hire Type Employee*Job ID 18283*Remote Eligible No*Date Posted [protected info]
Alternate Job Titles
SoC Verification Senior / Staff Engineer
ASIC Design Verification Senior / Staff Engineer
Digital Verification Senior / Staff Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in the trenches of SoC and IP verification, and you know the difference between a testbench that looks good in a demo and one that actually catches the corner case that would have bricked a chip three months into production. The verification lifecycle is not a checklist to you, it is a discipline, and you have strong opinions about what good coverage looks like versus coverage that just hits a number.
You are the kind of engineer who can stare at a waveform in Verdi for two hours, find the one transaction that should not have happened, trace it back through three clock domains, and explain what broke in a way that makes the RTL
designer say "oh, that makes sense." Protocols like PCIe, USB, and UCIe are not just acronyms to you. You have debugged them, you understand their timing quirks, and you know where the spec gets vague and real-world implementations diverge.
You are comfortable working in UVM, writing reusable components that other engineers will actually want to use, and automating the repetitive parts so you can focus on the hard problems. At Synopsys, you will work on real customer projects where your verification work directly impacts silicon that ships.
What You'll Be Doing
Execute the full RTL functional verification lifecycle for IP, subsystem, and SoC projects, from verification planning through coverage closure and signoff
Develop and maintain UVM-based verification environments, building reusable components and test infrastructures that scale across projects
Drive verification planning, define functional coverage models, write System Verilog Assertions, and execute strategies that ensure high-quality design deliverables
Debug complex design and verification issues using VCS and Verdi, performing root-cause analysis and coordinating with cross-functional teams
Collaborate with global Synopsys teams to deliver projects on schedule while meeting customer quality expectations
Interface directly with customer engineering teams to define project scope, establish verification strategies, and drive key deliverables (L3 and L4 roles)
Mentor junior verification engineers and contribute to continuous improvement of verification methodologies and best practices (L3 and L4 roles)
The Impact You Will Have
Catch critical design bugs before they reach silicon, saving months of respins and protecting customer schedules
Build verification infrastructure that gets reused across multiple projects, accelerating bring-up time for future designs
Drive coverage closure strategies that give customers confidence their silicon will work in the real world, not just in simulation
Shape verification methodologies and best practices that improve how the entire team approaches complex SoC and IP verification
Deliver customer projects that meet aggressive schedules without compromising quality, building trust and repeat business
Enable high-speed protocol implementations that power the next generation of AI, data center, and consumer products
What You'll Need
3+ years of hands-on experience in ASIC/SoC Design Verification, with strong understanding of end-to-end verification flows from planning through signoff
Proficiency in Verilog and System Verilog, with strong debugging and root-cause analysis skills using tools like VCS and Verdi
Solid expertise in UVM-based verification environments and experience developing reusable verification components
Experience developing System Verilog Assertions, functional coverage models, and coverage-driven verification methodologies
Strong scripting and automation skills using Python, Perl, or Shell scripting
Thorough understanding of AMBA protocols (AXI, AHB, APB) and experience verifying complex bus-based systems
Knowledge of high-speed interface protocols such as USB, PCIe, UCIe, DDR, or Ethernet is a strong plus
Who You Are
You can take a 500-page protocol spec, identify the verification-critical sections, and build a coverage plan that actually maps to what could go wrong in silicon
You approach debugging methodically, forming hypotheses and instrumenting the right signals rather than throwing print statements at a problem
You communicate technical tradeoffs clearly, whether explaining a coverage gap to a project lead or walking a customer through a verification strategy review
You care about the engineers who will inherit your testbench, writing code and documentation that makes their job easier
You stay current with verification methodologies and tools because you know the field moves quickly
The Team You'll Be Part Of
You will join the SSG-VN/DV team in Ho Chi Minh City, a collaborative group focused on delivering best-in-class design verification solutions for customer SoC, subsystem, and IP projects. The team works closely with global Synopsys engineering teams and interfaces directly with customers to define verification strategies, execute projects, and drive quality outcomes.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.