Design Verification Engineer

REQUIREMENT/ QUALIFICATION
• Bachelor's or Graduate Degree in: Computer Sciences, Electrical, or Computer Engineering.
• Have at least 2-5 years of proven experience
• Experience with Hardware Descriptive Languages (HDL) such as System Verilog, Verilog or VHDL is required.
• Understand digital hardware architectures and logic (State-machines, RAMs, Registers and bus architectures such as SPI or I2C).
• Must be self-driven & proactive with a desire to understand, learn more, do more.
• Excellent analytical and debugging skills with the ability to proactively solve issues is required.
• Verbal and written communication skills in English.
• Good understanding of ASIC design and verification methodologies/flows is a plus.
• Knowledge of verification methodologies such as UVM is a plus.
• The ability to work in a Linux shell environment and Linux scripting (CSH/TCL/Perl/Python) is a plus.
• Experience with silicon debugging which includes logic and Analog Blocks working together is a plus.
BENEFITS:
• Learn & work with world-class design engineers and IC products
• Dynamic, technological, global working environment
• Performance review to adjust salary and title/position.
• 13 months of salary, bonus paid twice a year and many other side benefits such as lunch allowance, healthcare program, annual health-screen, sport activities, gifts on special occasions etc.,