SoC Chipsets Design DFT Microarchitect

Seize the opportunity to work with the team responsible for providing technical leadership in the development of high quality and feature rich chipset products for PCs millions of people around the world will use. As part of the global Chipsets Silicon Group (CSG) within Silicon Engineering Group, you will be responsible for the Design-for-X (Test, Debug, Manufacturing) definition, implementation and verification for Chipset products As a SoC Chipsets Design DFT Microarchitect, a typical day may include, but is not limited to the technical disciplines on: DFT/DFD Microarchitecture - Drive product early technical readiness (TR), which require to understand customer requirement and plan for design definition solution across areas such as Memory BIST, Scan, TAP and other test or debug DFTs - Close handshake with DFx RTL design and Pre-Silicon Validation team to ensure quality of DFx feature implementation - Knowledge and hands-on experience on peripheral protocols such as I/O design protocols (SATA, PCIe, USB and others) is an added advantage DFx RTL Design - Perform DFx logic design RTL coding and integration into the Chipset SoC, with Memory BIST design experience is a must - Review and fix the DFx logic design to ensure all signal/clock connection, timing and etc. meet the design specifications with zero design errors - Strong communication skill to collaborate with geo-diverse teams (IP, SoC, Structural Design, IP, post-Silicon manufacturing) to analyze, debug, root cause and fix all DFx design issues DFx Pre-silicon Validation - Understand Design-for-Debug (DFD), Design-for-Test (DFT), Design-for-Manufacturing (DFM) or Design-for-Validation (DFV) features through design specs - Develop and document test plan and test sources. Ensure all the RTL Design being validated well to eliminate design flawless to customer. - Perform test verification and enhancement to ensure design quality and robustness - Drive test review with counterparts such as Pre-Silicon SoC, IP design, Post-Silicon Manufacturing, Board Design and other teams - Take ownership and partner with Manufacturing and Validation team to enable the post-Silicon defect screening, burn-in and system validation DFT Scan Design - Overseeing the Scan/ATPG definition, design, verification, and documentation for SoC development - Determining Scan architecture design, logic design, and system simulation - Defining module interfaces/formats for simulation - Performing logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, RTL coding, and SoC simulation - Contributing to the development of multidimensional designs involving the layout of complex integrated circuits - Performing all aspects of the SoC design Scan flow such as coverage analysis, setup and debug Spyglass-DFT or other ATPG tools, generate ATPG patterns via Mentor Graphic Tessent or other equivalent tools, RTL and GLS test validation to ensure quality design, debug and root cause stuckat and atspeed failure using Mentor GLS testbench in Synopsys VCS tools, and validate chain test in serial testbench - Driving post-Silicon High Volume Manufacturing (HVM) Team partnership to enable Scan DFT test capability - Collaborating with various stakeholders in architecture, IP, structural design, SoC RTL, and post-Silicon teams - Reviewing vendor capability to support development

We are looking for talented individual with the strengths on: - Excellent communication - Extremely organized - Strong technical leadership with great influencing skills - Collaborative team player - Passionate for design/tools and methodology - Commit and deliver to the organization - Motivated and Self-driven - strong drive to make a difference through technology Qualifications: - At least a Bachelor/Master of Engineering or Science degree in Electronic, Electrical or Computer Engineering - Familiar with UNIX, and well-versed in Verilog or C Programming - Strong hands-on DFT experience especially on Memory BIST, Scan, TAP and other industrial DFT design - Knowledge in RTL integration and validation methodologies - Knowledge in Design for Test, Debug, Manufacturing or Validation - Familiar with Scan design, methodology, coverage analysis and test validation - Ability to communicate well with counterparts and key stakeholders including cross-site partners

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



MY,02,Kulim;MY,07,Penang


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: [protected info]

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This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.