Verification Engineer

Worked on SoC level testbench and verification environment
Testbench architecture, coding and good understanding of design issues in RTL
Testbench generation, test vector creation, simulations, gate level simulations
Hands-on with System Verilog and Assertion-based verification methodology
At least 3 years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM,
UVM)
Simulation Tools:
NCSIM/VCS/ModelSim/Questa
Added Advantage:
Knowledge of RTL coding styles
Low power verification (UPF/CPF)
Experience on System C
Worked on protocols like AMBA, AHB/AXI, MIPI, PCI Express, SATA, USB.