Engineer / Senior Engineer - IC Verification

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Du Lịch
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Chăm sóc sức khỏe
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Mô tả Công việc
Develop & maintain verification environment for module and SOC level using UVM methodology
Create and debug test cases ; IP verification
Write and review verification plan
Use assertion based verification to verify module or SOC level
Perform code coverage analysis on module and SOC level
Yêu Cầu Công Việc
Degree / Master in Electrical / Electronic Engineering
2 years or above experience in the area of digital IC verification. Candidates with more years of experience may be considered for Senior Engineer position
Working experience from design to tape-out are essential
Experience in system Verilog and UVM verification methodology
Experience in using EDA tools from Cadence, Synopsys
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