Physical Implementation (Junior, Mid, Senior)

● Logic-level implementation and verification suitable for the development of SoC
● High-performance CPU, high-speed Interface IP such as Complex clock according to
structure, Timing Methodology
● UPF implementation and Low Power Specific SoC
● Design Flow, Signoff Methodology Development, and Implementation
● ASIC Frontend Implementation
● Physical aware synthesis STA, SDC Clean, Formal Verification
● Low Power Implementation, UPF design flow
● Big-Die Implementation (HPC/AI/Automotive)
● High Speed IP (DDR5/P, CIe/NANDPHY) Implementation
● Good communication with PD, DFT, and Customer