Design Verification Engineer (attractive benefit)

• Bachelor's degree in Electronics /Electrical Engineering or equivalent
• 1+ years of Experience as Design Verification Engineer or equivalent
• Good understanding of ASIC/SoC life cycle
• Experience in OVM/UVM methodologies using SV
• Experience with Full chip test plan development/modification
• Experience with Testbench development/modification, Test case development, coding, execution, bug analysis, Regressions, coverage analysis, Verification closure
• Experience in prevalent standards & Protocols viz. PCIe Gen3/4/5/USB3/DDR4/5, /Ethernet / CSI2 / I3C / AMBA
• Experience with Gate level simulations
• Experience in scripting
• Should have participated in multiple ASIC/SoC verification till tape out stage
• Good command of English
BENEFIT:
• 18 paid leaves/year (12 annual leaves and 6 personal leaves)
• Insurance plan based on full salary + 13th month salary
• Meal allowance of 730,000 VND/month
• 100% full salary and benefits as an official employee from the 1st day of working
• Medical benefit for employees and family
• Working in a fast-paced, flexible, and multinational working environment.
• Chance to travel onsite (in 49 countries)
• Free snacks, refreshment, and parking
• Internal training (Technical & Functional & English)
• Working with outstanding colleagues coming from top universities and top companies in Vietnam and foreign countries
• Friendly environment with flexible working hours
*** Note: We highly appreciate your interest in this position of HCL Vietnam. After reviewing all applications, only qualified candidates will be contacted for the next steps within 15 days from date of submission.