Kỹ Sư Thiết Kế Analog Layout Full-time 2024
Tập Đoàn Công Nghệ Đa Quốc Gia Synopsys
Hết hạn: 20/05/2024
- Chi tiết công việc
- Giới thiệu công ty
Vị trí công việc này hiện tại đã hết hạn nộp hồ sơ, bạn có thể tham khảo thêm một số công việc tương tự tại đây:
Position: Analog Layout Design Engineer
Level: Fresher/Junior
Location: Cau Giay Dist., Ha Noi; Hai Chau Dist., Da Nang
Introduction:
SNPS is the world number one IP provider with many experts from around the world and talented highly motivated Viet Nam engineering team.
Analog Mixed Signal (AMS) Team is responsible for the most advanced multi-dies interface technology: UCIe, AIB, OHBI. Our team is seeking for great Fresh and Junior level Engineer.
If you are a fresh graduated or have 1-2 years of experience in IC design, a great team player, willing to learn - this should be a perfect opportunity for you.
Opportunities:
SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team.
Professional, innovative, fair and fun working environment.
Competitive salary and benefit such as health Insurance, Football, Table tennis, Badminton, Yoga, Zumba Clubs.
Team building activity: Team trip, Family Day...
Opportunity to work with the complete design flow for a complicated Analog Mixed Signal Design from specification to silicon.
Clear career path of self-development to either Technical Experts or Manager
Travel to USA, Europe and Asia for training or on-site support.
Job Descriptions:
Candidates do not have to have experience on all the tasks below, there will be trainings to new engineers to adapt with Synopsys design and flows.
+ For freshers:
Will be trained to work on:
Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
Complete all design quality checks and data quality checks.
Report design and status to mentors and design leads.
Create documents that required by the given tasks.
+ For Juniors:
Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
Participate in building and enhancing layout flow for faster, higher quality design process.
Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
Do PERC verification for ESD/LUP checks.
Complete all design quality checks and data quality checks.
Work with Place and Route engineer to integrate analog layouts into top level.
Do design reviews across global team.
May collaborate in package design (Interposer design, RDL design)
Work closely with design team in Viet Nam and global to ensure the success of the whole product.
May join research programs to implement new ideas for future products and flows.
Skills Requirements:
+ For freshers:
BS in Electronics Engineering, Electromechanics, Telecommunications.
1/2 years of experience in related fields of IC designs is a plus (not required).
Interested in IC design and desire to persuade long term career path with IC design.
Good English communication verbally and in writing.
Good team player, willing to help others.
Highly responsible
Self-motivated
+ For Juniors:
BS in Electronics Engineering, Electromechanics, Telecommunications.
1+ years of experience in custom layout.
Familiar with Layout entry tools: Cadence, Synopsys
Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV
Understand basic semiconductor fabrication processes.
Understand MOSFET fundamentals.
Understand layout techniques for high speed, matching, Antenna, EMIR.
Understand layout techniques for ESD, Latchup, IO ring is a plus.
Experienced with writing layout review presentations and layout verification reports.
Good English communication
Good team player
Easy going, open & positive with feedback, eager to learn and grow.
Contact: Feel free to contact if you are interested in our opening positions. Please send your CV via Email: [protected info] or [protected info] or Contact via Phone/Zalo: [protected info]
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Level: Fresher/Junior
Location: Cau Giay Dist., Ha Noi; Hai Chau Dist., Da Nang
Introduction:
SNPS is the world number one IP provider with many experts from around the world and talented highly motivated Viet Nam engineering team.
Analog Mixed Signal (AMS) Team is responsible for the most advanced multi-dies interface technology: UCIe, AIB, OHBI. Our team is seeking for great Fresh and Junior level Engineer.
If you are a fresh graduated or have 1-2 years of experience in IC design, a great team player, willing to learn - this should be a perfect opportunity for you.
Opportunities:
SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team.
Professional, innovative, fair and fun working environment.
Competitive salary and benefit such as health Insurance, Football, Table tennis, Badminton, Yoga, Zumba Clubs.
Team building activity: Team trip, Family Day...
Opportunity to work with the complete design flow for a complicated Analog Mixed Signal Design from specification to silicon.
Clear career path of self-development to either Technical Experts or Manager
Travel to USA, Europe and Asia for training or on-site support.
Job Descriptions:
Candidates do not have to have experience on all the tasks below, there will be trainings to new engineers to adapt with Synopsys design and flows.
+ For freshers:
Will be trained to work on:
Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
Complete all design quality checks and data quality checks.
Report design and status to mentors and design leads.
Create documents that required by the given tasks.
+ For Juniors:
Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
Participate in building and enhancing layout flow for faster, higher quality design process.
Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
Do PERC verification for ESD/LUP checks.
Complete all design quality checks and data quality checks.
Work with Place and Route engineer to integrate analog layouts into top level.
Do design reviews across global team.
May collaborate in package design (Interposer design, RDL design)
Work closely with design team in Viet Nam and global to ensure the success of the whole product.
May join research programs to implement new ideas for future products and flows.
Skills Requirements:
+ For freshers:
BS in Electronics Engineering, Electromechanics, Telecommunications.
1/2 years of experience in related fields of IC designs is a plus (not required).
Interested in IC design and desire to persuade long term career path with IC design.
Good English communication verbally and in writing.
Good team player, willing to help others.
Highly responsible
Self-motivated
+ For Juniors:
BS in Electronics Engineering, Electromechanics, Telecommunications.
1+ years of experience in custom layout.
Familiar with Layout entry tools: Cadence, Synopsys
Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV
Understand basic semiconductor fabrication processes.
Understand MOSFET fundamentals.
Understand layout techniques for high speed, matching, Antenna, EMIR.
Understand layout techniques for ESD, Latchup, IO ring is a plus.
Experienced with writing layout review presentations and layout verification reports.
Good English communication
Good team player
Easy going, open & positive with feedback, eager to learn and grow.
Contact: Feel free to contact if you are interested in our opening positions. Please send your CV via Email: [protected info] or [protected info] or Contact via Phone/Zalo: [protected info]
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Thông tin chung
- Ngày hết hạn: 20/05/2024
- Thu nhập: Thỏa thuận
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