Layout Design, Senior / Staff Engineer - 18157

Alternate Job Titles
Senior Custom Layout Engineer
IC Layout Staff Engineer
Memory Layout Staff Engineer
Custom IC Layout Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in custom layout design, and you know that the difference between a chip that performs beautifully and one that barely meets spec often comes down to decisions made at the polygon level. You understand FinFET technology not as a buzzword but as a set of real constraints that shape every routing decision, every contact placement, every boundary condition you navigate.
You are the kind of engineer who does not just run DRC and hope for clean results. You anticipate where violations will appear, you know which rules are soft and which are absolute, and you debug LVS mismatches by reading netlists and layouts side by side until the problem reveals itself. When a circuit designer hands you a schematic and says "make this fast," you already have three layout strategies in mind, each with different tradeoffs.
You think in layers and design rules, but you communicate in outcomes. Working with verification engineers does not slow you down because you have learned to speak their language. Scripting is not a chore for you but a force multiplier. You write Perl or TCL to automate repetitive work so you can focus on layout decisions that actually require judgment.
At Synopsys, you will work on memory and standard cell designs that power silicon inside everything from AI accelerators to automotive systems.
What You'll Be Doing
Design custom layouts for memory leafcells and standard cells using Custom Compiler, optimizing for performance, area, and power across FinFET nodes
Run physical verification flows including DRC, LVS, and ERC using ICV tools, debugging violations and ensuring clean signoff
Collaborate with circuit designers to translate schematics into layouts that meet electrical specifications and design intent
Develop automation scripts in Perl, Shell, or TCL to streamline layout tasks and verification flows
Optimize existing layouts for speed, area, or power based on performance analysis and downstream feedback
Participate in design reviews, providing layout feasibility input and identifying potential issues early
Document layout methodologies and best practices to support knowledge sharing across the team
The Impact You Will Have
Deliver memory and standard cell layouts that meet aggressive performance targets and enable next-generation silicon products
Reduce design cycle time through automation and efficient verification workflows, accelerating time to tapeout
Improve silicon yield and reliability by catching layout-induced issues before fabrication
Contribute to Synopsys IP offerings that customers depend on for critical chip designs
Mentor junior layout engineers and share techniques that raise the quality bar across the team
Drive continuous improvement in layout methodologies as technology nodes advance
Strengthen cross-functional collaboration between layout, circuit design, and verification teams
What You'll Need
You have 2+ years of hands-on experience in custom layout design with standard cells, memory blocks, or analog/mixed-signal circuits
You bring deep familiarity with FinFET technology nodes and advanced process design challenges
You are proficient with Custom Compiler and ICV for layout and physical verification
You have a Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field
You know how to write and debug scripts in Perl, Shell, or TCL to automate layout and verification tasks
Experience with boundary conditions, guard rings, well isolation, and noise mitigation techniques is a strong plus
Who You Are
You catch the misaligned contact or missing via before it becomes a showstopper three weeks later
You communicate layout constraints clearly to circuit designers and project leads who do not think in polygons
You approach verification failures methodically, breaking down complex issues into root causes rather than guessing at fixes
You are comfortable learning new tools, nodes, and design rules without needing everything handed to you
You take ownership from initial floorplan to final signoff without losing track of what you committed to deliver
The Team You'll Be Part Of
You will join a focused engineering team in Ho Chi Minh City working on custom layout and physical design for Synopsys IP products. The team collaborates closely with circuit designers and verification engineers, and the work you do directly impacts IP that ships to customers worldwide.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.