Senior Design Verification Engineers (Hybrid)

Develop and implement verification plans to ensure the functional correctness of VLSI designs before they are fabricated.
Create and maintain verification environments using advanced verification methodologies such as UVM (Universal Verification Methodology), OVM (Open Verification Methodology), or VMM (Verification Methodology Manual).
Write and debug test cases, manage regression test suites, and analyze coverage reports to ensure comprehensive testing of VLSI designs.
Collaborate with design engineers to identify and resolve design issues detected during the verification process.
Enhance existing verification tools and processes to improve efficiency and effectiveness of the verification workflow.
Mentor junior verification engineers and lead verification teams to achieve project goals within designated timelines.
Stay updated with the latest trends and developments in VLSI verification methodologies and technologies.
Essential Skills
In-depth knowledge of digital circuit design and verification.
Expertise in SystemVerilog and any of the major verification methodologies like UVM, OVM, or VMM.
Ability to develop verification plans that align with project scope and design complexity.
Strong debugging skills and familiarity with simulation tools such as Cadence Xcelium, Mentor Questa, or Synopsys VCS.
Desirable Skills
Experience with formal verification tools and methodologies.
Knowledge of ASIC or FPGA design flow.
Familiarity with advanced verification features such as assertions and functional coverage.
Leadership skills with experience managing small teams or leading verification projects.