Job Title:
Senior Application Engineer(Verification tools)
Location:
HCM
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, IP integration, and simulation and analysis, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
Job Description:
Provide advanced technical support for EDA Design & Verifications tools (VCS, Verdi, Spyglass, Certitude, Z01X..), addressing complex customer issues and ensuring customer satisfaction.
Take ownership on Tool migrations, bring up verification environments as well as Verification IPs.
Collaborate with worldwide Application Engineers, R&D teams and Customers to understand requirements, address escalations, and ensure successful adoption of solutions and tool development.
Actively contributes to strategies that secure and expand market share by understanding competitive landscape and building strong customer relationships.
Develop and share technical documentation, lead knowledge transfer, and mentor junior team members.
Key skills & experience:
1+ years of Design and Verification or Application Engineer on Verification Field
Good on Verilog, UVM, System Verilog, VHDL and UPF is a plus.
Good expertise in Design and Verification, Verification IPs(AMBA VIP), Static and/or Dynamic Verification.
Excellent communication skills in English; able to work cross-functionally and cross-regionally.
Passion on using new tools and features as well as AI tool related.
Ability to manage relationships with both customers and internal stakeholders.
Demonstrated leadership in mentoring, onboarding, or leading technical initiatives.
Thông tin chung