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Mô tả công việc
Synopsys Viet Nam welcomes passionate and talented senior students to join and experience the professional working environment and learn more about ASIC Digital Design.
• Position: ASIC Digital Design Intern
• Location: Ho Chi Minh city
• Internship type: 6-month full-time, tentative from Nov/2024
1. Internship Program:
This is a 6-month internship program, you will learn:
- ASIC design flow, RTL design flow, and Design Verification flow
- RTL coding using Verilog, SystemVerilog
- Testbenches writing, RTL verification, Universal Verification Methodology (UVM)
- Design for Test (Synthesis, Static Timing Analysis, Scan insertion, ATPG)
- Presentation skills, teamwork, task management, etc...
Yêu cầu
- Final year students, major in Electronics Engineering, Telecommunications, Mechatronics, Automation & Control, Computer Science or other related majors. (not yet graduated during the internship period, expecting to graduate in 2025).
- GPA >= 3.0/4 or 7.0/10 (Latest updated).
- Available for 6-month full-time internship, tentative from Nov, 2024.
- Basic knowledge of Digital design is a plus.
- Interested in IC design and desire to pursue long-term career path of IC design.
- Good English communications (4 skills)
- Self-study, researching and presentation skills
- Highly accountable, patient, hard-working.
- Good at both individual work and teamwork skills.
Quyền lợi
- Monthly internship allowances.
- Be trained fundamental knowledge of ASIC digital design and essential soft skills to become a professional engineer.
- Be supported graduation thesis: be provided interesting topics and guided by dedicated engineers.
- Have the opportunity to work in real IC design projects with Synopsys.
- Have chances to experience a real working environment and enjoy team activities.
- Have the opportunity to become official Synopsys employees after completing the internship program.
Thông tin chung
- Ngày hết hạn: 11/11/2024
- Thu nhập: Thỏa thuận