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Mô tả công việc
Responsibilities
Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. Demonstrate ownership from DFT logic, pre-silicon verification, to co-work with test engineers post silicon.
Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support post-silicon test team.
Yêu cầu
Minimum qualifications:
Bachelor's degree in
Electrical Engineering, a related field, or equivalent practical experience.
5 years of experience in DFT specification definition architecture and insertion.
3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent).
Experience with ASIC DFT synthesis, STA, simulation, and verification flow.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
Preferred qualifications:
Master's degree in Electrical Engineering, or a related field.
Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
Experience in SoC cycles, including silicon bring-up and silicon debug activities.
Experience in fault modeling.
Thông tin khác
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.
The AI and Infrastructure team works on the world's toughest problems, redefining what's possible and the possible easy. We empower Google customers by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Googler Cloud customers, and billions of Google users worldwide. We're at the center of amazing work at Google by being the "flywheel" that enables our advanced AI models, delivers computing power across global services, and offers platforms that
developers use to build services.
In AI and Infrastructure, we shape the future of hyperscale computing by inventing and creating world-leading future technology, and drive global impact by contributing to Google infrastructure, from software to hardware (including building Vertex AI for Google Cloud). We work on complex technologies at a global scale with key players in the AI and systems space. Join a team of talented individuals who not only work together to keep data centers operating efficiently but also create a legacy of driving innovation by building some of the most complex systems technologies.
Thông tin chung
- Ngày hết hạn: 14/11/2025
- Thu nhập: Thỏa thuận
