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Mô tả công việc
Mô tả Công việc
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Responsibilities:
Work in a Digital and Verification Development team during the development and validation of complex digital mix signals for high-speed interface IP.
Test planning, checklist, Coverage and Assertion planning
Hands on experience in creating detailed Verification Environment from Functional Specifications
Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
Writing test cases, checkers, and coverage that implement the verification test plan.
Debug of simulations, including those of real signals modeled using SV for analog
RTL, GLS & Co-simulations & coverage closure
Participate in technical reviews and contribute actively
Participate in customer support with bring-up of IP in customer simulation environment
Follow and improve development process ensuring high quality output.
Yêu cầu
Yêu Cầu Công Việc
Requirements:
BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
5+ years of experience in Design Logic Verification
Strong skill with VCS/Verdi simulation tools, Formal verification tool (vc_formal)
Knowledge of UPF, UVM(Universal Verification Methodology) and SVA (System-Verilog Assertion) is a plus
Strong debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus
Highly responsible, result oriented
Good English communication both verbally and in writing
Great team player, willing to support others
Self-motivated and highly enthusiasm in technology and solving problems
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Quyền lợi
Laptop
Chế độ bảo hiểm
Du Lịch
Phụ cấp
Chế độ thưởng
Chăm sóc sức khỏe
Đào tạo
Tăng lương
Nghỉ phép năm
CLB thể thao
Thông tin khác
Bằng cấp:
Đại học
Độ tuổi:
Không giới hạn tuổi
Thông tin chung
- Ngày hết hạn: [protected info]
- Thu nhập: Cạnh tranh
