Design Implementation Engineer

- The Role
• In this role, you will be responsible for ASIC implementation, including synthesis, floorplanning, place and route, and timing closure, on our cutting edge ARMv8 based server on chip solutions (X-Gene) that will be the backbone of future data centers. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology (3nm and 5nm) nodes available in the industry.
- What The Team Wants You To Know
• You should be a motivated person and a team player who is ready to work in a startup-like culture. Our mantra is "Ampere First!" and as part of the team you should be thinking about how I can contribute to make a better Server product.
- What You'll Do:
• Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, function ECO, placement, CTS, route and other sign-off
• Run physical synthesis on large and medium-sized blocks
• Implement and verify other aspects of netlist generation like scan-insertion, clock-gating checks, power-domain checks, etc
• Develop mid-end to back-end implementation flows on synthesis, placement, CTS, Route, timing analysis, eco-generation, etc
• Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners
• Perform timing closure across all corners to ensure successful tape out following our aggressive deadlines
• Generate and implement functional ECO
• Run Logic Equivalent Check (LEC) from RTL to pre-layout/post-layout netlist