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Mô tả công việc
University Internships & New Graduate Programs (Freshers) Da Nang, Vietnam
Summary
• eSilicon has revolutionized the chip business by partnering with tier-one suppliers to streamline the IC design and manufacturing processes, bringing our customers' chips to market faster. eSilicon has a world-class custom IP team with a successful track record of first-time silicon success and demonstrated ability to provide niche IP and design services at leading-edge process nodes.
• Our Analog Mixed Signal IP Team is seeking for Junior FrontEnd Design/Verification to join our talented team.
• We are working on most advanced product on the market. Join us and make a difference.
Opportunities
• Work with highly experienced global team and talented highly motivated Viet Nam engineering team
• Work in a professional, innovative and fun environment.
• Working on most competitive designs such as: High Band Width Memory (HBM) PHY, High Speed PAM4 56G/128G Serdes, High Band Width Die to Die PHY..
• Opportunity to get in touch with the complete flow of a real complicated Analog Mixed Signal Design: From Specification - RTL/Synthesis - Analog Circuit/Layout - Place & Route - Timing & Physical Sign Off - Packaging - Signal/Power Integrity - Silicon Bring Up.
• Chance to work with the latest possible technology nodes (16nm/14nm/10nm/7nm/5nm) from all foundries.
• Clear career path of self-development to either Technical Expert or Design Leader/Manager
• Travel to USA, Europe and Asia for demo shows, customer engagement, training and on site support.
Benefits
• Competitive salary
• Very good insurance program for engineer and family members
• Strong internal training programs of softskills
• Participate in valuable conferences to learn and share knowledge with IC design community
Responsibilities
• Create the test checklist base on design specification.
• Implement vectors to verify the design block/IP.
• Building and develop behavior model, testbench.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Work closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product.
• May join research programs to implement new ideas for future products and flows
Yêu cầu
• BS in Electronics Engineering, Electromechanics, Telecommunication, Automation.
• 1+ year experience with Logic Verification or Fresh graduate students with hands on experiences with Verilog.
• Is a plus:
o Experience verifying digital logic at the Register Transfer Level (RTL) using Verilog/SystemVerilog.
o Familiarity with VMM/UVM-based functional verification concepts and methodologies, as they apply to design for test.
o Have knowledge about EDA Verification, UNIX commands, Script languages (c shell, bash shell, Perl ...)
• Locate in Da Nang city
• Good English communication
Quyền lợi
Training with Trainers from U.S
Thông tin chung
- Ngày hết hạn: 18/04/2019
- Thu nhập: Thỏa thuận
