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Mô tả công việc
- Middle End design - SDC including debug, Logic Synthesis, STA
- LSI logic and IP Design and functional verification
Yêu cầu
- Graduated College, University in Electronics, Telecommunications, Computer Science,Computer Engineering, Information Technology, Mathematics.
- Have experience for 3-5 years.
- Had experience in Electronics engineering with logic design, verification.
- Have good knowledge of RTL design by VerilogHDL or VHDL
- Design Compiler, PrimeTime, VCS, Formality, Spyglass experience.
- Have a solid understanding of logic specification and verification method.
- Have good working attitude, serious, diligence, proactive approach, team work spirit and creativity.
- Have capability of leading team.
- Long term working commitment
- English communication skill mandatory. Japanese language skill is plus.
- Expected TOEIC 450 points and more.
Quyền lợi
-Training opportunity in Japan
- Lunch and gasoline allowances
- 3 times of bonus per year (for each 6 months, 12 months and Tet bonus)
- Health care insurance from Bao Viet
- 12 Annual leave days/year.
- Working day from Monday to Friday, 8:00 am to 5:00 pm
- Good working environment
Thông tin khác
-Bạn nào quan tâm xin vui lòng điền vào form ứng tuyển bằng tiếng Anh tại website [protected info] Sanei Resume form và nộp tới địa chỉ [protected info] Please download Sanei CV form from [protected info] Sanei Resume form and send it to [protected info]
Thông tin chung
- Ngày hết hạn: 30/04/2018
- Thu nhập: Cạnh tranh
